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W631GG6KB
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
ODTLcnw
Command
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
VALID
ODT
ODTH4
ODTLon
ODTLoff
RTT
t AONmin
Rtt_WR
t ADCmin
t AOFmin
Rtt_Nom
ODTLcwn4
t ADCmax
t ADCmax
t AOFmax
DQS, DQS#
DQ
WL
Din
b
Din
b+1
Din
b+2
Din
b+3
TRANSITIONING
DON'T CARE
Notes:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
Figure 80 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
ODTLcnw
Command
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
VALID
ODT
RTT
ODTH4
ODTLon
t AONmin
ODTLoff
Rtt_WR
t AOFmin
DQS, DQS#
ODTLcwn4
t ADCmax
t AOFmax
DQ
WL
Din
b
Din
b+1
Din
b+2
Din
b+3
TRANSITIONING
DON'T CARE
Note:
1. Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH4 = 4 is exactly satisfied.
Figure 81 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 4 clock cycles
Publication Release Date: Dec. 09, 2013
Revision A05
- 87 -
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